A well-known cause of failure in electronic integrated circuits is exposure to large and/or sudden electrostatic discharge (ESD). A built-up electrostatic charge may be quickly discharged when the charged device comes into contact with an integrated circuit, for example, when portions of the circuit are connected to power supplies, including ground. The discharge can cause damage to the integrated circuit as a result of dielectric breakdown of oxides and/or other thin films, and also by higher levels of conduction through relatively small areas of the integrated circuit arising from reverse breakdown of p-n junctions on the circuit.
Electrostatic discharge (ESD) may have an effect on the reliability of integrated circuits. Further, as the size of integrated circuits is reduced, ESD tolerance may also be reduced. In particular, as a result of higher current density and lower voltage tolerance, as ICs become smaller and/or faster, the susceptibility of their protection circuits to damage may increase. Further, as lightly doped drain (LDD) regions become shallower than source/drain diffusion regions, for a given current level, there may be a greater current density in the LDD region, which means there may be more localized heating. Still further, silicided source/drain diffusion areas may also lead to current localization by concentrating current flow at the surface of devices, as well as, reducing the ballasting resistance needed to distribute the current. Additionally, thinner gate oxides of MOS transistors may be more susceptible to high-field stress, for example, dielectric breakdown.
In particular, in a mixed-voltage application, some components or integrated circuits may operate at a lower voltage level, while other peripheral components or other integrated circuits may operate at a higher voltage level. As a result, there may be chips with different power supply voltages coexisting in the same system. Input/output (I/O) circuits may be designed to be tolerant of various input voltages. Further, chip-to-chip interface I/O circuits, including ESD protection circuits, may be designed to avoid electrical overstress on the transistors and/or to reduce or prevent undesirable leakage current paths between the chips.
As an example, a conventional power clamp may be used to ensure than an ESD path between a supply voltage VDD and a ground voltage VSS, is triggered by an ESD event. For voltages higher than the supply voltage VDD or lower than the ground voltage VSS, the power clamp may provide a discharge path, for example, to ground.
Conventional power clamps include MOS transistors, NPN, PNP bipolar transistors, diodes, thyristors, or field transistors. In order to discharge ESD events without damaging an internal circuit or the ESD protection circuit itself, an ESD protection scheme should have a low voltage turn-on and high current drive. In particular, if the first breakdown voltage or trigger voltage is higher than the breakdown voltage of the gate dielectric of a MOS transistor, the ESD protection scheme may fail to protect the internal circuit and the internal circuit may be destroyed. Further, if a response time of the ESD triggering is delayed, the ESD protection scheme may fail to protect a high speed or higher frequency integrated circuit, due to an initial build-up of high voltage or large current.